Research
IEEE Xplore, 2026 · 2026
ECG denoising
A Verilog implementation of a cascaded filter architecture that cleans a real-time ECG signal in hardware, with a reported 19.92 dB improvement in signal-to-noise ratio.
Specification
As built, not as pitched
- Reported gain
- +19.92 dB SNR
- Implementation
- Verilog RTL
- Design and analysis
- MATLAB
- Verification
- ModelSim, captured ECG
- Preserved feature
- QRS complex
- Published
- IEEE Xplore, Mar 2026
- With
- Navya, Sphatika, Megha
- Organisation
- IEEE Xplore, 2026
- Year
- 2026
- Stage
- Published
- Role
- RTL design, Filter architecture, Signal validation
- Delivered
- Cascaded Verilog filter chain, MATLAB analysis, ModelSim verification
An ECG is a small signal in a noisy room: baseline wander from breathing, mains hum from the wiring, and muscle noise from the patient. Diagnoses are made on the shape of a wave that is easy to lose.
The work specifies a cascade of filters — baseline removal, mains rejection and smoothing — designed in MATLAB and then written in Verilog so it can run on acquisition hardware instead of a desktop. Simulated against captured ECG data in ModelSim, the chain reports a 19.92 dB improvement in signal-to-noise ratio while preserving the QRS complex.
Published through IEEE Xplore in March 2026 with Navya, Sphatika and Megha. The DOI and author record will be linked here once verified.
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